Design of a Low-Power 1.65 Gbps Data Channel for HDMI Transmitter

摘要

This paper presents a design of low power data channel for application inHigh Definition Multimedia Interface (HDMI) Transmitter circuit. The input is10 bit parallel data and output is serial data at 1.65 Gbps. This circuit usesonly a single frequency of serial clock input. All other timing signals arederived within the circuit from the serial clock. This design has dedicatedlines to disable and enable all its channels within two pixel-clock periodsonly. A pair of disable and enable functions performed immediately afterpower-on of the circuit serves as the reset function. The presented design isimmune to data-dependent switching spikes in supply current and pushes them inthe range of serial frequency and its multiples. Thus filtering requirementsare relaxed. The output stage uses a bias voltage of 2.8 volts for a receiverpull-up voltage of 3.3 volts. The reported data channel is designed using UMC180 nm CMOS Technology. The design is modifiable for other inter-board serialinterfaces like USB and LAN with different number of bits at the parallelinput.